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EEM 223 - Logic Circuits Laboratory

Faculty of Engineering and Natural Sciences · Electrical & Electronics Engineering (English 30%) · Undergraduate

ECTS: 2 T+P+L: 0+0+2 Compulsory
Coordinator: Doç. Dr. Mohammed VADİ
Instructors: Doç. Dr. Mohammed VADİ

Course Objective

The objective of the Logic Design Laboratory course is to provide hands-on experience with digital circuits, enabling students to design, implement, and test combinational and sequential logic systems effectively.

Course Content

Digital electronics lab. covers the design and application of digital electronic circuits, including combinational and sequential logic circuits.
 

Required Resources

Mohammed VADİ Notes

Recommended Resources

Anil K. Maini, Digital Electronics - Principles, Devices and Applications, John Wiley & Sons, 2007.

Explanations

There will be in-class weekly quiz, in addition to one midterm exam, and final exam.

1.     Most quizzes will be pre-announced at least one lecture in advance. No make-up quizzes will be given.  However, the lowest quiz will not be counted toward your final grade.

2.     Exam dates are shown in the previous mentioned table.  Refer to the syllabus to see the topics that will make up the material for each exam. With a valid written excuse and making immediate arrangements with the instructor, a missed exam might be replaced with the grade of the final exam and/or the average grade of all tests (including final) and/or quizzes.

3.     The final exam is Practical at Lab.  The date and time of the final exam will be scheduled by Assist. Prof. Mohammed VADİ

Rules

  1. Attendance: It is the university policy that attendance is compulsory.  A student missing more than 15% of the total allocated course hours will receive a WF (Withdrawal While Failing).
  2. Getting Help: Students are encouraged to consult their instructor during office hours, or by appointment. However, before seeking help from anyone, make sure you read your lecture notes and textbook. See the examples similar to the problem in question then try to do the problem yourself. It should be emphasized that students who miss a class without a valid written and/or legitimate excuse will not be offered a one-on-one lecture discussion during office hours to substitute the missed class.
  3. Academic Misconduct will not be tolerated.  You are expected to submit your own work. Copying, cheating or plagiarism, when detected, will result in an FF grade in the course for all who are involved (i.e. it does not matter if somebody copied your homework, project etc., you are guilty as well).

The Istanbul Sabahattin Zaim University affirms the importance of integrity and respecting the work of each individual.  As an institution of higher education, the university views academic integrity as an educational as well as judicial issue.  Academic violations include (but not limited to) the following: plagiarism, inappropriate collaboration, dishonesty in examinations, dishonesty in papers, work done for one course and submitted to another, deliberate fascination of data, etc. See the Student Handbook at http://www.izu.edu.tr/handbook/ for more details.

Course Learning Outcomes

  1. Outlines the formal procedures for the analysis and design of combinational circuits.
  2. Outlines the formal procedures for analyzing and designing clocked (synchronous) sequential circuits.
  3. The map method is also used to simplify digital circuits constructed with AND OR, NAND, or NOR gates.
  4. Covers the map method for simplifying Boolean expressions.
  5. Presents the various binary systems suitable for representing information in digital systems.
  6. Introduces the basic postulates of Boolean algebra and shows the correlation between Boolean expressions and their corresponding logic diagrams.
  7. Deals with various sequential circuit components such as registers, shift registers, and counters.

Core Area Distribution

(46) Mathematics and Statistics%30 (48) Computing%30 (52) Engineering and Engineering Trades%40

Teaching Methods

Exercise and PracticePresentationExperiment - Test / Lab/ Workshop / Field PracticeProblem SolvingProject Based Learning (Including Field Work)

Assessment & Evaluation

HomeworkPerformance Assignment ( Lab / Workshop / Field Work / Seminar / Presentation / Completion Study / ThesisProject / DesignTesting (Essay / Tests: True-Falls, multiple-choice, short answer, matching)

ECTS / Workload

ActivityQuantityDuration (h)Total Workload
Course Duration (Including Exam Week)16232
Out of Class Study Period16116
Midterm000
Quiz000
Assignment10220
Practice000
Final000

Course Schedule

WeekSubjectPreparation
1Preparation to lab. and groups formationThe Breadboard
2Verification of the truth tables of Logic Gates/Universal Gates using TTL ICsTTL Kapıları
3Design of Code Converters (Binary To Gray and Gray To Binary conversion)İkiliden Gri ve Griya İkili Dönüşüm
4Design and implementation of Half/Full Adder and Subtractor using logic gates/universal gatesYarım / Tam Toplayıcı Yarım / Tam Subtraktörü
5Design of Multiplexers/Demultiplexers, Encoders and DecodersÇoklayıcı / De Çoklayıcılar, Enkoderler ve Dekoderlerin
6Design and implementation of one bit, two bit Magnitude ComparatorsBir bit, iki bit Büyüklük Karşılaştırıcı
7Implementation and Verification of Truth Tables of RS, JK, T and D Flip-FlopsRS, JK, T ve D Flip-Flop
8No Lab due to Mid-Term ExamsAra Sınavlar Haftası
9Design and implementation Shift RegistersKaydırma Kayıtları
10Design and implementation of Sequence GeneratorDizi Jeneratörünün
11Design and implementation of Asynchronous CountersAsenkron Sayıcıları
12Design and implementation of Synchronous CountersSenkron Sayıcıları
13Design and implementation of Ring Counter and Johnson CounterHalka Sayaç ve Johnson Sayaçları
14Compensatory Lab.Telafi Laboratuvarı
15Lab. Final ExamLab. Final Sınavı
16IZU Final ExamsİZÜ Final Sınavları