Faculty of Engineering and Natural Sciences · Computer Engineering · Undergraduate
ECTS: 5 T+P+L: 2+0+1 Departmental Elective
Coordinator: Prof. Dr. Tarık ÖZKUL
Required Resources
1. Digital Systems Design Using Verilog Book by Byeong Kil Lee, Charles H Roth, and Lizy John
2. FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version
Teaching Methods
ExpressionQuestion-AnswerExercise and PracticePresentationGuided PracticeExperiment - Test / Lab/ Workshop / Field PracticeProblem SolvingProject Based Learning (Including Field Work)
Assessment & Evaluation
HomeworkPerformance Assignment ( Lab / Workshop / Field Work / Seminar / Presentation / Completion Study / ThesisProject / DesignTesting (Essay / Tests: True-Falls, multiple-choice, short answer, matching)
ECTS / Workload
| Activity | Quantity | Duration (h) | Total Workload |
|---|---|---|---|
| Course Duration (Including Exam Week) | 16 | 32 | 512 |
| Out of Class Study Period | 5 | 5 | 25 |
| Midterm | 1 | 1 | 1 |
| Quiz | 3 | 3 | 9 |
| Assignment | 5 | 14 | 70 |
| Practice | 5 | 5 | 25 |
| Final | 1 | 1 | 1 |
Course Schedule
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